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  4. Scalable hardware architecture for real-time execution of biomimetic spiking neural networks
 
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Scalable hardware architecture for real-time execution of biomimetic spiking neural networks

Journal
Neuromorphic Computing and Engineering
ISSN
2634-4386
Date Issued
2025
Author(s)
Zapata, Mireya
Centro de investigación en Mecatrónica y Sistemas Interactivos
Bernardo Vallejo-Mancero
Jordi Madrenas
Type
journal-article
DOI
10.1088/2634-4386/ae24a5
URL
https://cris.indoamerica.edu.ec/handle/123456789/9886
Abstract
Replicating the operation of biological neurons using electronic hardware is of significant interest for engineering and biomedical applications. Spiking neural network (SNN) models are especially suited, as they exhibit temporal dynamics and local synaptic plasticity, closely mimicking biological neural function. To enable biological interaction, real-time response, and the ability to explore and deploy multiple neural models becomes also necessary. In this work, the hardware emulator of evolving neural spiking systems, an efficient, fully digital architecture intended for real-time execution of SNNs, is reported. Based on single instruction multiple data computation, an array of simple but programmable processing elements is controlled by a sequencer dispatching common instructions. Local distributed memory avoids data bottlenecks, enabling parallel parameter updates and interconnect reconfiguration. The address-encoded spikes are decoded by local associative memories that can be modified on the fly, thus supporting evolvable networks. A synchronous ring topology based on fast point-to-point serial links enables multi-node systems with minimal latency and excellent scalability. A control node controls and configures the ring nodes, drives the system execution, and monitors the processed data. The hardware is supported by a user-friendly custom set of tools that performs a simple and fast compilation of neural/synaptic algorithms and network topology on a host computer. The results of field-programmable gate array implementation are reported. Multimodel real-time execution of proof-of-concept networks demonstrates the potential of the proposed architecture.
Subjects
  • address event represe...

  • evolvable neural netw...

  • FPGA-based hardware e...

  • neuromorphic engineer...

  • on-chip distributed m...

  • real-time spiking neu...

  • SIMD

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Apr 15, 2026
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