Acceleration of Evolutionary Grammar Using an MISD Architecture Based on FPGA and Petalinuxs

The evolutionary grammars are part of the optimization methods and searching for solutions based on the biological evolution postulates. The proposed technique is based on the genetic recombination’s concept and could be used to automatically generate programs in any programming language according to the specified grammar. The objective of this work is to design and evaluate a hardware acceleration solution for a Java evolutionary grammar software application, performing modifications in the data processing phase using an MISD (Multiple Instruction Single Data) architecture. The implementation is performed on a platform that integrates the programmability of an ARM processor along with the programmable logic of an FPGA with a custom Linux embedded operative system like Petalinux. The tests carried out allow determining the viability of the project, the results show that the parallelized stage is faster than the original solution, and the whole system can be implemented in a SoC. © 2021, The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG.